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Description of  RISCV Interrupts & Platform Level Interrupt Controller

Published 3/2024 Created by Benix Samuel Vincent Theogaraj MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch Genre: eLearning | Language: English | Duration: 15 Lectures ( 2h 5m ) | Size: 971 MB What you'll learn: Understand privilege levels, traps and control and status registers Platform Level Interrupt Controller Specification Sample implementation of PLIC module on FE310 SoC Demonstration of interrupt generation & handling in RISC-V assembly Requirements: Brief knowledge on any processor like interrupts, interrupt priority & interrupt handling would help Description: Who this course is for: Embedded system developers and RISC-V enthusiasts