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Description of  Formal Verification of Floating-Point Hardware Design: A Mathematical Approach Ed 2

This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts IIII (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V. Read more